Static Timing Analysis

Project : VEML6031X00
Build Time : 06/06/23 15:24:49
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ClockBlock/clk_bus_glb_ff ClockBlock/clk_bus_glb_ff UNKNOWN UNKNOWN N/A
CyILO CyILO 100.000 kHz 100.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Clock To Output Section
+ ClockBlock/clk_bus_glb_ff
Source Destination Delay (ns)
\I2C_1:I2C_FF\/sda_out SDA_1(0)_PAD:out 24.751
Type Location Fanout Instance/Net Source Dest Delay (ns)
i2ccell F(I2C,0) 1 \I2C_1:I2C_FF\ \I2C_1:I2C_FF\/clock \I2C_1:I2C_FF\/sda_out 1.000
Route 1 \I2C_1:sda_x_wire\ \I2C_1:I2C_FF\/sda_out SDA_1(0)/pin_input 7.818
iocell2 P12[1] 1 SDA_1(0) SDA_1(0)/pin_input SDA_1(0)/pad_out 15.933
Route 1 SDA_1(0)_PAD SDA_1(0)/pad_out SDA_1(0)_PAD:out 0.000
Clock Clock path delay 0.000
\I2C_1:I2C_FF\/scl_out SCL_1(0)_PAD:out 24.669
Type Location Fanout Instance/Net Source Dest Delay (ns)
i2ccell F(I2C,0) 1 \I2C_1:I2C_FF\ \I2C_1:I2C_FF\/clock \I2C_1:I2C_FF\/scl_out 1.000
Route 1 \I2C_1:Net_643_0\ \I2C_1:I2C_FF\/scl_out SCL_1(0)/pin_input 7.814
iocell1 P12[0] 1 SCL_1(0) SCL_1(0)/pin_input SCL_1(0)/pad_out 15.855
Route 1 SCL_1(0)_PAD SCL_1(0)/pad_out SCL_1(0)_PAD:out 0.000
Clock Clock path delay 0.000